The present invention relates to a method of manufacturing a semiconductor device having isolating oxide layers.
Generally, an isolating oxide layer is provided between any two functions allocated on a semiconductor substrate for inhibiting the effect of parasitic capacitance from the other functions in a semiconductor device. The isolating oxide layer may include that formed by local oxidation of silicon (hereinafter referred to as LOCOS) and a film formed in a trench by the use of an anisotropic etching technique. An oxide film formed in a shallow trench by the use of a shallow trench isolation (STI) technique is also available.
After the shallow trench has been formed, the trench is filled with an isolating oxide layer uniformly. However, the oxide layer formed has a varying thickness. For eliminating the non-uniformity, planarization is applied. The planarization is performed substantially uniformly throughout the surface and when variation in thickness is too large, they may hardly be compensated. Accordingly, a (pre-etching) process for etching the oxide layer is widely used for removing relatively taller regions of the isolating oxide layer to minimize surface undulations before the planarization process. In a common practice of the oxide layer etching, the oxide layer is etched until the nitride layer is exposed as shown in the cross sectional view of FIG. 22D. This is followed by removal of a resist layer for planarizing the surface and eliminating undulations.
In Japanese Laid-Open Patent Publication 11-312730, the isolating oxide layer deposited on a cell pattern of nitride silicon layer is etched so as to be substantially similar height to the upper surface of the nitride layer. In this case, the oxide layer on a peripheral area of the cell pattern of the nitride layer may be left.
In Japanese Laid-Open Patent Publication 11-145090, a method of manufacturing a semiconductor device having two-steps polishing process is disclosed. The one polishing process is applied for polishing down to a polishing stopper layer which has been provided and then another polishing process is carried out for removing the polishing stopper layer.
However, when the oxide layer has been etched down to the upper side of the nitride layer, the nitride layer is exposed and then polished in the planarization process, resulting in undesirable reduction of the film thickness of the nitride layer. Also, the pre-etched regions of the oxide layer are again etched by the oxide layer etching process and thus becomes thinner than the other regions. The subsequent planarization process will cause the isolating oxide layer adjacent the pre-etched regions to be stepped down sharply from the edge of each trench as shown in FIG. 23D.
In the Japanese Laid-Open Patent Publication 11-312730, during the semiconductor device manufacturing method, the oxide layer on the nitride layer is substantially flush with the oxide layer filling the trench. Accordingly, if the oxide layer on the nitride layer is relatively thin, it may excessively be polished down about the nitride layer during the planarization process.
In the other semiconductor device manufacturing method disclosed in the Japanese Laid-Open Patent Publication 11-145090, the stopper layer has to be prepared before the planarization process. The preparation of the stopper layer requires another step of forming it. In the etching process before the planarization process, as the oxide layer is etched down to the stopper layer, no etching adjustment will be allowed.
Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can minimize the thinning of the nitride layer in the planarization process and inhibits the peripheral area of the nitride layer from being excessively be polished down.
In accordance with one aspect of the present invention, there is provided a method of manufacturing a semiconductor device. The method includes following the steps of:
(a) providing a semiconductor substrate;
(b) forming a trench in the semiconductor substrate;
(c) depositing an oxide layer to fill the trench and cover the surface of the semiconductor substrate;
(d) etching the oxide layer so as to leave a thickness of the oxide layer; and
(e) planarizing the surface of the semiconductor substrate.
In another aspect of the present invention, there is provided a method of manufacturing a semiconductor device. The method includes following the steps of:
(a) providing a semiconductor substrate;
(b) forming a nitride layer on the semiconductor substrate;
(c) patterning the nitride layer;
(d) etching the semiconductor substrate while masking with a patter of the nitride layer to form a trench;
(e) depositing an oxide layer to fill the trench and cover the nitride layer;
(f) forming a resist layer on the oxide layer;
(g) patterning the resist layer;
(h) etching the oxide layer on the nitride layer; and
(i) planarizing the oxide layer.
In addition the step of etching the oxide layer permits a thickness of the oxide layer to be left on the nitride layer.
In a further aspect of the present invention, during the step of depositing the oxide layer, the oxide layer may be deposited to a controlled thickness determined from the thickness of the oxide layer left during the step of etching the oxide layer.
In a still further aspect of the present invention, during the step of depositing the oxide layer, the oxide layer may be deposited to a controlled thickness determined from a ratio of area between the nitride layer peripheral area including the nitride area itself and the oxide layer filling the trench.
In a yet further aspect of the present invention, during the step of etching the oxide layer, the oxide layer may be etched to leave a thickness of the oxide layer determined from a ratio of area between the nitride layer peripheral area including the nitride area itself and the oxide layer filling the trench.
In a yet further aspect of the present invention, during the step of depositing the oxide layer, the oxide layer may be deposited to a controlled thickness determined corresponding to the distance from the center of a wafer where the semiconductor substrates are provided.
In a yet further aspect of the present invention, during the step of etching the oxide layer, the oxide layer may be etched to a controlled depth determined corresponding to the distance from the center of a wafer where the semiconductor substrates are provided.
In a yet further aspect of the present invention, during the step of etching the oxide layer, the oxide layer may be etched at an area distanced from the trench.
In a yet further aspect of the present invention, the area to be etched may be determined from a ratio of area between the nitride layer peripheral area including the nitride area itself and the oxide layer filling the trench.
In a yet further aspect of the present invention, during the step of planarizing, the planarizing processes may be performed several times.
In a yet further aspect of the present invention, during the step of planarizing, the planarizing processes with different degrees of polishing may be performed several times.
In a yet further aspect of the present invention, the method may further include a step of measuring the thickness of the oxide layer left on the nitride layer to determine the degree of polishing for the succeeding planarizing process between any two planarizing processes in the planarizing step.
According to the method of this invention, the compensating thickness of the oxide layer may be left on the nitride layer during the etching process of the oxide layer prior to the planarization process. Accordingly, the thinning of the nitride layer can be minimized in the planarization process and the peripheral area of the nitride layer can be inhibited from being excessively polished down.
According to the method of this invention, the compensating thickness of the oxide layer may be left on the nitride layer during the etching process of the oxide layer prior to the planarization process. Accordingly, the thinning of the nitride layer can be minimized in the planarization process and the peripheral area of the nitride layer can be inhibited from being excessively polished down.
According to the method of this invention, the oxide layer may be deposited to a controlled thickness determined from the compensating thickness of the oxide layer left in the step of etching the oxide layer. As a result, the compensating thickness of the oxide layer on the nitride layer can easily be provided as a margin.
According to the method of this invention, the oxide layer may be deposited to a controlled thickness determined from the ratio of area between the nitride layer peripheral area including the nitride layer itself and the oxide layer filling the trench. Therefore, any area to be not over-polished can be protected.
According to the method of this invention, the oxide layer may be etched to leave a thickness of the oxide layer determined from the ratio of area between the nitride layer peripheral area including the nitride layer itself and the oxide layer filling the trench. Therefore, the over-polishing can selectively be made.
According to the method of this invention, the oxide layer may be deposited to a controlled thickness determined corresponding to the distance from the center of the wafer. Therefore, the thickness of the oxide layer can be uniform after the step of etching the oxide layer while discrepancy in the etching rate between different locations on the wafer is favorably compensated.
According to the method of this invention, the oxide layer to be etched to a controlled depth determined corresponding to the distance from the center of the wafer. Therefore, the thickness of the oxide layer can be uniform after the step of etching the oxide layer while discrepancy in the etching rate between different locations on the wafer is favorably compensated.
According to the method of this invention, the oxide layer to be etched at the area distanced from the trench. Therefore, the over-polishing can selectively be carried out.
According to the method of this invention, the area to be etched may be determined from the ratio of area between the nitride layer peripheral area including the nitride layer itself and the oxide layer filling the trench. Therefore, the over-polishing can be made with different degrees of polishing determined depending on the pattern of the nitride layer.
According to the method of this invention, the planarizing processes may be performed several times. Therefore, the degree of polishing can be controlled at each planarization process.
According to the method of this invention, the planarizing processes may be performed with different degree of polishing. For example, a combination of the planarization for having a higher flatness and the planarization with a higher selectivity for the nitride layer can produce a higher flatness on the finished surface while inhibiting the nitride layer from being excessively polished.
According to the method of this invention, the degree of polishing at the next step to be determined by measuring the thickness of the oxide layer left on the nitride layer between any two planarizing processes. Therefore, the overpolishing can be avoided.